1. Field of the Invention
The present invention relates, in general, to a method and circuit for programming a phase-change memory array to a set state.
2. Description of the Related Art
Phase-change random access memories (PRAMs) are non-volatile memory devices that store data using a phase-change material, such as a chalcogenide (e.g., Ge—Sb—Te (GST)), the electric resistance of which varies upon a phase transition between two states that is caused by a change in temperature. PRAMs have many of the advantages of both volatile memories such as dynamic random access memories (DRAMs) and non-volatile memories, at a generally lower power consumption.
If current flows through a phase-change material during a write operation, for example, the phase-change material may change back and forth between a crystalline state and an amorphous state. As an example, a phase-change material may be heated to its melting point by applying a relatively high current pulse to the phase-change material for a relatively short duration of time. The phase-change material may then be rapidly cooled, which changes the phase-change material to a highly resistive, amorphous state. If the phase-change material layer in the rest state is cooled by applying a relatively low current pulse, the phase-change material may be changed to a lower resistive, crystalline state.
Thus, the final state depends on the amount of current and/or duration that current flows through the phase-change material. A relatively large current flowing through the phase-change material for a relatively short time (referred to as a ‘reset current’ or reset current pulse’) changes the phase-change material from a crystalline state to an amorphous state. The amorphous state may be referred to as a ‘reset state’ corresponding to data having a logic level value of “1”. A current smaller than the reset current that is flowing through the phase-change material for a relatively longer duration changes the phase-change material from the amorphous state back to the crystalline state. The crystalline state may be referred to as a ‘set state’ corresponding to data having a logic level value of “0”.
The resistance of the phase-change material in the reset state is greater than the resistance of the phase-change material in the set state. A memory cell that is initially in a set state may thus be changed to a reset state by flowing a reset current through the phase-change material to heat the phase-change material above its melting temperature, and then quickly quenching the heated phase-change material, as described above. The memory cell initially in a reset state may be changed to a set state by flowing a set current through the phase-change material to heat the phase-change material above its crystallizing temperature, maintaining the current for a given period of time, and then cooling the phase-change material.
FIG. 1 is a graph illustrating a conventional current pulse used for writing data to a phase-change material. In a conventional method of writing data, as shown in FIG. 1, a relatively high current pulse may be applied to a phase-change material for a relatively short duration to melt the phase-change material. The phase-change material is then cooled fast to change the state of the phase-change material to an amorphous state (i.e., a reset state). Alternatively, a relatively lower current pulse is applied to the phase-change material for a relatively longer duration (as shown in FIG. 1) to heat the phase-change material at a temperature that is greater than the crystallizing temperature of the phase-change material, so as to change the phase-change material to a crystalline state (i.e., a set state).
However, in a memory array having a plurality of phase-change memory cells, parasitic resistances may vary among the individual or groups of phase-change memory cells, depending on cell arrangements within the memory array. Further, signal loads may vary on lines connected to the phase-change memory cells, and reset currents may vary among the phase-change memory cells due to, for example, differences in manufacturing processes as the area of the memory array increases. If the reset currents vary between or among different memory cells, set currents also vary among the memory cells.
Consequently, the level or amount of the set current pulses used to change the memory cells to a set state may vary between memory cells of the memory array. This may be undesirable, since it is impossible to change all the memory cells in the memory array to a set state using one set current. In other words, if one set current is applied, some of the memory cells may change to a set state, but other memory cells may actually change to a reset state. Also, resistance values may vary among the memory cells that do change to the set state. This may cause errors in phase-change memory array operation.
FIG. 2 is a graph showing the relationship between current applied to the phase-change memory cells and the resistance of the phase-change memory cells. Referring to FIG. 2, three memory cells (A, B, and C) exemplifying given memory cells of the phase-change memory array will be described as an example of the relationship between the current applied to phase-change memory cells and the resistance of the phase-change memory cells. The memory cells A, B, and C each have different reset/set current curves. The memory cell A is a ‘high’ set current cell, the memory cell B is an ‘intermediate’ set current cell, and the memory cell C is a ‘low’ set current cell. The graph of FIG. 2 illustrates that the amounts or levels of current needed to change the memory cells A, B, and C to a set resistance state vary among memory cells A, B, and C.
If a current corresponding to a voltage (i) shown in FIG. 2 is applied to the memory cells, the memory cell A can change to a set resistance state (as it is within a set window or that enables memory cell A to be changed to a set state), but the memory cells B and C remain in a reset state (resistance values too high). Further, the memory cells B and C have different reset resistances. As a result, since the phase-change cells of the array require different currents to change to a set state, one set current cannot be used to change all the memory cells of the array into a set state.